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| 1997, 2000 data sheet description the m pd75p3018a replaces the m pd753017as internal mask rom with a one-time prom, and features expanded rom capacity. the m pd75p3018a inherits the function of the m pd75p3018, and enables high-speed operation at a low supply voltage of 1.8 v. because the m pd75p3018a supports programming by users, it is suitable for use in evaluation of systems in development stages using the m pd753012a, 753016a, or 753017a, and for use in small-scale production. the following document describes further details of the functions. please make sure to read this document before starting design. m pd753017 users manual : u11282e features compatible with m pd753017a memory capacity: ? prom : 32768 8 bits ? ram : 1024 4 bits can operate in the same power supply voltage as the mask version m pd753017a ? v dd = 1.8 to 5.5 v lcd controller/driver ordering information part number package m pd75p3018agc-3b9 80-pin plastic qfp (14 14 mm, resin thickness 2.7 mm) m pd75p3018agc-8bt 80-pin plastic qfp (14 14 mm, resin thickness 1.4 mm) m pd75p3018agk-be9 80-pin plastic tqfp (fine pitch) (12 12 mm, resin thickness 1.05 mm) m pd75p3018agk-9eu 80-pin plastic tqfp (fine pitch) (12 12 mm, resin thickness 1.00 mm) caution mask-option pull-up resistors are not provided in this device. document no. u11917ej2v0ds00 (2nd edition) date published july 2000 n cp (k) printed in japan m pd75p3018a mos integrated circuit 4-bit single-chip microcontroller the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. the mark shows major revised points.
m pd75p3018a 2 data sheet u11917ej2v0ds00 function outline item function instruction execution time ? 0.95, 1.91, 3.81, 15.3 m s (main system clock: at 4.19 mhz operation) ? 0.67, 1.33, 2.67, 10.7 m s (main system clock: at 6.0 mhz operation) ? 122 m s (subsystem clock: at 32.768 khz operation) internal memory prom 32768 8 bits ram 1024 4 bits general-purpose register ? 4-bit operation: 8 4 banks ? 8-bit operation: 4 4 banks input/output port cmos input 8 on-chip pull-up resistor connection can be specified by using software: 23 cmos input/output 16 cmos output 8 also used for segment pins n-ch open-drain input/output 8 13 v breakdown voltage total 40 lcd controller/driver ? segment number selection : 24/28/32 segments (can be changed to cmos output port in unit of 4; max. 8) ? display mode selection : static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias) 1/3 duty (1/3 bias), 1/4 duty (1/3 bias) timer 5 channels: ? 8-bit timer/event counter: 3 channels (can be used for 16-bit timer/event counter, carrier generator, timer with gate) ? basic interval timer/watchdog timer: 1 channel ? watch timer: 1 channel serial interface ? 3-wire serial i/o mode ... msb or lsb can be selected for transferring first bit ? 2-wire serial i/o mode ? sbi mode bit sequential buffer (bsb) 16 bits clock output (pcl) ? f , 524, 262, 65.5 khz (main system clock: at 4.19 mhz operation) ? f , 750, 375, 93.8 khz (main system clock: at 6.0 mhz operation) buzzer output (buz) ? 2, 4, 32 khz (main system clock: at 4.19 mhz operation or subsystem clock: at 32.768 khz operation) ? 2.93, 5.86, 46.9 khz (main system clock: at 6.0 mhz operation) vectored interrupt ? external : 3 ? internal : 5 test input ? external : 1 ? internal : 1 system clock oscillator ? ceramic or crystal oscillator for main system clock oscillation ? crystal oscillator for subsystem clock oscillation standby function stop/halt mode power supply voltage v dd = 1.8 to 5.5 v package ? 80-pin plastic qfp (14 14 mm) ? 80-pin plastic tqfp (fine pitch) (12 12 mm) m pd75p3018a 3 data sheet u11917ej2v0ds00 contents 1. pin configuration (top view) ............................................................................................... .4 2. block diagram ............................................................................................................... ............ 5 3. pin functions ............................................................................................................... ............... 6 3.1 port pins ................................................................................................................... ................................ 6 3.2 non-port pins ............................................................................................................... ............................ 8 3.3 pin input/output circuits ................................................................................................... ...................... 10 3.4 recommended connection for unused pins ...................................................................................... .. 12 4. switching function between mk i mode and mk ii mode ....................................... 13 4.1 difference between mk i mode and mk ii mode ................................................................................. .... 13 4.2 setting of stack bank selection register (sbs) .............................................................................. ..... 14 5. differences between m pd75p3018a and m pd753012a, 753016a, and 753017a ....... 15 6. memory configuration ........................................................................................................ .. 16 6.1 program counter (pc) ........................................................................................................ ..................... 16 6.2 program memory (prom) ....................................................................................................... ................ 16 6.3 data memory (ram) ........................................................................................................... ...................... 19 7. instruction set ............................................................................................................. ............ 20 8. one-time prom (program memory) write and verify ............................................. 30 8.1 operation modes for program memory write/verify ............................................................................ 3 0 8.2 program memory write procedure .............................................................................................. ........... 31 8.3 program memory read procedure ............................................................................................... .......... 32 8.4 one-time prom screening ..................................................................................................... ................ 33 9. electrical specifications ................................................................................................... .34 10. package drawings ........................................................................................................... ........ 48 11. recommended soldering conditions .............................................................................. 52 appendix a. m pd75316b, 753017a and 75p3018a function list .......................................... 54 appendix b. development tools ............................................................................................... 56 appendix c. related documents ............................................................................................... 60 m pd75p3018a 4 data sheet u11917ej2v0ds00 1. pin configuration (top view) ? 80-pin plastic qfp (14 14 mm) m pd75p3018agc-3b9, 75p3018agc-8bt ? 80-pin plastic tqfp (fine pitch) (12 12 mm) m pd75p3018agk-be9, 75p3018agk-9eu note connect the v pp directly to v dd during normal operation. pin identifications bias : lcd power supply bias control p70-p73 : port7 bp0-bp7 : bit port 0-7 pcl : programmable clock buz : buzzer clock pto0-pto2 : programmable timer output 0-2 com0-com3 : common output 0-3 reset : reset d0-d7 : data bus 0-7 s0-s31 : segment output 0-31 int0, 1, 4 : external vectored interrupt 0, 1, 4 sb0, sb1 : serial bus 0,1 int2 : external test input 2 sck : serial clock kr0-kr7 : key return 0-7 si : serial input lcdcl : lcd clock so : serial output md0-md3 : mode selection 0-3 sync : lcd synchronization p00-p03 : port0 ti0-ti2 : timer input 0-2 p10-p13 : port1 v dd : positive power supply p20-p23 : port2 v lc0 -v lc2 : lcd power supply 0-2 p30-p33 : port3 v pp : programming power supply p40-p43 : port4 vss : ground p50-p53 : port5 x1, x2 : main system clock oscillation 1, 2 p60-p63 : port6 xt1, xt2 : subsystem clock oscillation 1, 2 s11 80 s10 79 s9 78 s8 77 s7 76 s6 75 s5 74 s4 73 s3 72 s2 71 s1 70 s0 69 reset 68 p73/kr7 67 p72/kr6 66 p71/kr5 65 p70/kr4 64 p63/kr3 63 p62/kr2 62 p61/kr1 61 1 s12 s13 s14 s15 2 3 4 s16 5 s17 6 s18 7 s19 8 s20 9 s21 10 s22 11 s23 12 s24/bp0 13 s25/bp1 14 s26/bp2 15 s27/bp3 16 s28/bp4 17 s29/bp5 18 s30/bp6 19 s31/bp7 20 com0 21 com1 22 com2 23 com3 24 bias 25 v lc0 26 v lc1 27 v lc2 28 p40/d0 29 p41/d1 30 p42/d2 31 p43/d3 32 vss 33 p50/d4 34 p51/d5 35 p52/d6 36 p53/d7 37 p00/int4 38 p01/sck 39 p02/so/sb0 40 60 p60/kr0 x2 x1 v pp note xt2 59 58 57 56 xt1 55 v dd 54 p33/md3 53 p32/md2 52 p31/sync/md1 51 p30/lcdcl/md0 50 p23/buz 49 p22/pcl/pto2 48 p21/pto1 47 p20/pto0 46 p13/ti0 45 p12/int2/ti1/ti2 44 p11/int1 43 p10/int0 42 p03/si/sb1 41 m pd75p3018a 5 data sheet u11917ej2v0ds00 2. block diagram port0 p00 to p03 4 port1 p10 to p13 4 port2 p20 to p23 4 port3 p30/md0 to p33/md3 4 port4 p40/d0 to p43/d3 4 port5 p50/d4 to p53/d7 4 port6 p60 to p63 4 port7 p70 to p73 4 lcd controller /driver s0 to s23 24 s24/bp0 to s31/bp7 8 com0 to com3 4 v lc0 to v lc2 3 bias lcdcl/p30/md0 sync/p31/md1 f lcd v pp v dd reset v ss cpu clock f stand by control x2 x1 xt2 xt1 system clock generator main sub clock divider clock output control fx/2 n pcl/pto2/p22 general reg. ram data memory 1024 x 4 bits bank sbs sp (8) alu decode and control timer/event counter #1 pto1/p21 intt1 timer/event counter #2 pto2/p22/pcl intt2 basic interval timer/ watchdog timer intbt timer/event counter #0 ti0/p13 intt0 clocked serial interface si/sb1/p03 intcsi interrupt control int0/p10 ti1/ti2/ p12/int2 pto0/p20 tout0 watch timer intw buz/p23 f lcd so/sb0/p02 sck/p01 tout0 int1/p11 int2/p12/ti1/ti2 int4/p00 kr0/p60 to kr7/p73 bit seq. buffer (16) 8 program counter (15) prom program memory 32768 x 8 bits cy tout0 m pd75p3018a 6 data sheet u11917ej2v0ds00 3. pin functions 3.1 port pins (1/2) pin name i/o alternate function function 8-bit after reset i/o circuit i/o type note 1 p00 input int4 this is a 4-bit input port (port0). input p01 to p03 are 3-bit pins for which an internal p01 sck pull-up resistor connection can be specified m pd75p3018a 7 data sheet u11917ej2v0ds00 3.1 port pins (2/2) pin name i/o alternate function function 8-bit after reset i/o circuit i/o type note 1 p60 i/o kr0 this is a programmable 4-bit i/o port (port6). ? input m pd75p3018a 8 data sheet u11917ej2v0ds00 3.2 non-port pins (1/2) pin name i/o alternate function function after reset i/o circuit type note 1 ti0 input p13 external event pulse input to timer/event counter input -c ti1, ti2 p12/int2 pto0 output p20 timer/event counter output input e-b pto1 p21 pto2 p22 pcl p22 clock output buz p23 optional frequency output (for buzzer or system clock trimming) sck i/o p01 serial clock i/o input m pd75p3018a 9 data sheet u11917ej2v0ds00 3.2 non-port pins (2/2) pin name i/o alternate function function after reset i/o circuit type s0-s23 output segment signal output note 1 g-a s24-s31 output bp0-bp7 segment signal output note 1 h-a com0-com3 output common signal output note 1 g-b v lc0- v lc2 power source for lcd driver bias output output for external split resistor cut high impedance lcdcl note 2 i/o p30/md0 clock output for driving external expansion driver input e-b sync note 2 i/o p31/md1 clock output for synchronization of external expansion driver input e-b notes 1. the v lcx (x = 0, 1, 2) shown below are selected as the input source for the display outputs. s0-s31: v lc1 , com0-com2: v lc2 , com3: v lc0 2. these pins are provided for future system expansion. currently, only p30 and p31 are used. m pd75p3018a 10 data sheet u11917ej2v0ds00 3.3 pin input/output circuits the input/output circuits for the m pd75p3018as pins are shown in abbreviated form below. (1/2) in v dd p-ch n-ch v dd p-ch n-ch out data output disable in v dd p-ch in/out p.u.r. enable data p.u.r. type d output disable p.u.r. : pull-up resistor type a v dd p-ch p.u.r. enable p.u.r. p.u.r. : pull-up resistor in v dd p-ch in/out p.u.r. enable data p.u.r. type d output disable p.u.r. : pull-up resistor type b cmos standard input buffer push-pull output that can be set to high impedance output (with both p-ch and n-ch off). schmitt trigger input with hysteresis characteristics. type a type d type e-b type b type b-c type f-a m pd75p3018a 11 data sheet u11917ej2v0ds00 (2/2) type f-b type h-a type m-c type g-a type g-b type m-e output disable v dd p-ch n-ch in/out data v dd p-ch p.u.r. enable p.u.r. output disable (n) output disable (p) p.u.r. : pull-up resistor in type g-a voltage controller type d seg data output disable bit port data v dd p-ch in/out p.u.r. enable data p.u.r. output disable p.u.r. : pull-up resistor n-ch p-ch out n-ch v lc0 v lc1 com data v lc2 n-ch n-ch p-ch pull-up resistor operated only when executing input instructions (when pins are low level, current flows from v dd to pins). output disable data n-ch in/out (+13 v withstand voltage) note v dd p-ch input instruction note p.u.r. n-ch n-ch v lc2 n-ch p-ch out v lc0 v lc1 seg data (+13 v withstand voltage) m pd75p3018a 12 data sheet u11917ej2v0ds00 3.4 recommended connection for unused pins pin recommended connection p00/int4 connect to v ss or v dd p01/sck connect to v ss or v dd via a resistor individually p02/so/sb0 p03/si/sb1 connect to v ss p10/int0, p11/int1 connect to v ss or v dd p12/ti1/ti2/int2 p13/ti0 p20/pto0 input : connect to v ss or v dd via a resistor individually p21/pto1 output : leave open p22/pto2/pcl p23/buz p30/lcdcl/md0 p31/sync/md1 p32/md2, p33/md3 p40/d0-p43/d3 connect to v ss p50/d4-p53/d7 p60/kr0-p63/kr3 input : connect to v ss or v dd via a resistor individually p70/kr4-p73/kr7 output : leave open s0-s23 leave open s24/bp0-s31/bp7 com0-com3 v lc0 -v lc2 connect to v ss bias connect to v ss only when v lc0 to v lc2 are all not used. in other cases, leave open. xt1 note connect to v ss xt2 note leave open note when subsystem clock is not used, specify sos.0 = 1 (indicates that internal feedback resistor is disconnected). m pd75p3018a 13 data sheet u11917ej2v0ds00 4. switching function between mk i mode and mk ii mode setting a stack bank selection (sbs) register for the m pd75p3018a enables the program memory to be switched between mk i mode and mk ii mode. this function is applicable when using the m pd75p3018a to evaluate the m pd753012a, 753016a, or 753017a. when the sbs bit 3 is set to 1 : sets mk i mode (supports mk i mode for m pd753012a, 753016a, and 753017a) when the sbs bit 3 is set to 0 : sets mk ii mode (supports mk ii mode for m pd753012a, 753016a, and 753017a) 4.1 difference between mk i mode and mk ii mode table 4-1 lists points of difference between the mk i mode and the mk ii mode for the m pd75p3018a. table 4-1. difference between mk i mode and mk ii mode item mk i mode mk ii mode program counter pc 13-0 pc 14-0 pc 14 is fixed at 0 program memory (bytes) 16384 32768 data memory (bits) 1024 4 stack stack bank selectable via memory banks 0 to 3 no. of stack bytes 2 bytes 3 bytes instruction bra !addr1 instruction not available available calla !addr1 instruction instruction call !addr instruction 3 machine cycles 4 machine cycles execution time callf !faddr instruction 2 machine cycles 3 machine cycles supported mask roms when set to mk i mode: when set to mk ii mode: m pd753012a, 753016a, and 753017a m pd753012a, 753016a, and 753017a caution the mk ii mode supports a program area exceeding 16 kbytes for the 75x and 75xl series. therefore, this mode is effective for enhancing software compatibility with products that have a program area of more than 16 kbytes. with regard to the number of stack bytes during execution of subroutine call instructions, the usable area increases by 1 byte per stack compared to the mk i mode when the mk ii mode is selected. however, when the call !addr and callf !faddr instructions are used, the machine cycle becomes longer by 1 machine cycle. therefore, if more emphasis is placed on ram use efficiency and processing performance than on software compatibility, the mk i mode should be used. m pd75p3018a 14 data sheet u11917ej2v0ds00 4.2 setting of stack bank selection register (sbs) use the stack bank selection register to switch between mk i mode and mk ii mode. figure 4-1 shows the format for doing this. the stack bank selection register is set using a 4-bit memory manipulation instruction. when using the mk i mode, be sure to initialize the stack bank selection register to 10xxb note at the beginning of the program. when using the mk ii mode, be sure to initialize it to 00xxb note . note set the desired value for xx. figure 4-1. format of stack bank selection register cautions 1. sbs3 is set to 1 after reset input, and consequently the cpu operates in mk i mode. when using instructions for mk ii mode, set sbs3 to 0 and set mk ii mode before using the instructions. 2. when using mk ii mode, execute a subroutine call instruction and an interrupt instruction after reset input and after setting the stack bank selection register. sbs3 sbs2 sbs1 sbs0 f84h address 3 2 1 0 sbs 0 0 1 1 0 1 0 1 symbol stack area specification memory bank 0 memory bank 1 memory bank 2 memory bank 3 0 be sure to set bit 2 to 0. 0 1 mk ii mode mk i mode mode selection specification m pd75p3018a 15 data sheet u11917ej2v0ds00 5. differences between m pd75p3018a and m pd753012a, 753016a, and 753017a the m pd75p3018a replaces the internal mask rom in the m pd753012a, 753016a, and 753017a with a one-time prom and features expanded rom capacity. the m pd75p3018as mk i mode supports the mk i mode in the m pd753012a, 753016a, and 753017a and the m pd75p3018as mk ii mode supports the mk ii mode in the m pd753012a, 753016a, and 753017a. table 5-1 lists differences among the m pd75p3018a and the m pd753012a, 753016a, and 753017a. be sure to check the differences among these products before using them with proms for debugging or prototype testing of application systems or, later, when using them with a mask rom for full-scale production. for the cpu functions and internal hardwares, refer to m pd753017 user's manual (u11282e) . table 5-1. differences between m pd75p3018a and m pd753012a, 753016a, and 753017a item m pd753012a m pd753016a m pd753017a m pd75p3018a program counter 14 bits 15 bits program memory (bytes) mask rom one-time prom during 12288 16384 16384 16384 mk i mode during 12288 16384 24576 32768 mk ii mode data memory ( 4 bits) 1024 mask options pull-up resistor for yes (can be specified whether to incorporate or not) no (cannot incorporate) port4 and port5 lcd split resistor feedback resistor yes (can be specified whether to use or not) no (used) for subsystem clock wait time yes (can be specified either 2 17 /f x or 2 15 /f x ) note no (fixed at 2 15 /f x ) note during reset pin configuration pin nos. 29 to 32 p40 to p43 p40/d0 to p43/d3 pin nos. 34 to 37 p50 to p53 p50/d4 to p53/d7 pin no. 50 p30/lcdcl p30/lcdcl/md0 pin no. 51 p31/sync p31/sync/md1 pin nos. 52 and 53 p32, p33 p32/md2, p33/md3 pin no. 57 ic v pp other noise resistance and noise radiation may differ due to the different circuit sizes and mask layouts. note for 2 17 /f x , during 6.0 mhz operation is 21.8 ms, and during 4.19 mhz operation is 31.3 ms. for 2 15 /f x , during 6.0 mhz operation is 5.46 ms, and during 4.19 mhz operation is 7.81 ms. caution noise resistance and noise radiation are different in prom and mask roms. in transferring to mask rom version from the prom version in a process between prototype development and full production, be sure to fully evaluate the mask rom versions cs (not es). m pd75p3018a 16 data sheet u11917ej2v0ds00 6. memory configuration 6.1 program counter (pc) ... 15 bits this is a 15-bit binary counter that stores program memory address data. bit 15 is valid during mk ii mode. but pc14 is fixed at zero during mk i mode, and the lower 14 bits are all valid. figure 6-1. configuration of program counter 6.2 program memory (prom) ... 32768 8 bits the program memory consists of 32768 8-bit one-time prom. the program memory address can be selected as shown below by setting the stack bank selection (sbs) register. mk i mode mk ii mode usable address 0000h to 3fffh 0000h to 7fffh figures 6-2 and 6-3 show the addressing ranges for the program memory and branch instruction and the subroutine call instruction, during mk i and mk ii modes. pc14 pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 pc fixed at zero during mk i mode m pd75p3018a 17 data sheet u11917ej2v0ds00 figure 6-2. program memory map (mk i mode) remark for instructions other than those noted above, the br pcde and br pcxa instructions can be used to branch to addresses with changes in the pcs low-order 8 bits only. mbe mbe mbe mbe mbe mbe mbe rbe rbe rbe rbe rbe rbe rbe internal reset start address (high-order 6 bits) internal reset start address (low-order 8 bits) intbt/int4 start address (high-order 6 bits) intbt/int4 start address (low-order 8 bits) int0 start address (high-order 6 bits) int0 start address (low-order 8 bits) int1 start address (high-order 6 bits) int1 start address (low-order 8 bits) intcsi start address (high-order 6 bits) intcsi start address (low-order 8 bits) intt0 start address (high-order 6 bits) intt0 start address (low-order 8 bits) intt1, intt2 start address (high-order 6 bits) intt1, intt2 start address (low-order 8 bits) reference table for geti instruction 0000h 0002h 0004h 0006h 0008h 000ah 000ch 007fh 0080h 07ffh 0800h 0fffh 1000h 1fffh 2000h 2fffh 3000h 3fffh callf !faddr instruction entry address branch addresses for the following instructions ?br bcde ?br bcxa ?br !addr ?call !addr branch/call address by geti br $addr instruction relative branch address (?5 to ?, +2 to +16) brcb !caddr instruction branch address brcb !caddr instruction branch address brcb !caddr instruction branch address brcb !caddr instruction branch address 765 0 0020h m pd75p3018a 18 data sheet u11917ej2v0ds00 figure 6-3. program memory map (mk ii mode) caution to allow the vectored interrupts 14-bit start address (noted above), set the address within a 16k area (0000h to 3fffh). remark for instructions other than those noted above, the br pcde and br pcxa instructions can be used to branch to addresses with changes in the pcs low-order 8 bits only. mbe mbe mbe mbe mbe mbe mbe rbe rbe rbe rbe rbe rbe rbe internal reset start address (high-order 6 bits) internal reset start address (low-order 8 bits) intbt/int4 start address (high-order 6 bits) intbt/int4 start address (low-order 8 bits) int0 start address (high-order 6 bits) int0 start address (low-order 8 bits) int1 start address (high-order 6 bits) int1 start address (low-order 8 bits) intcsi start address (high-order 6 bits) intcsi start address (low-order 8 bits) intt0 start address (high-order 6 bits) intt0 start address (low-order 8 bits) intt1, intt2 start address (high-order 6 bits) intt1, intt2 start address (low-order 8 bits) reference table for geti instruction 0000h 0002h 0004h 0006h 0008h 000ah 000ch 1fffh 2000h 2fffh 3000h 3fffh 4000h 4fffh 5000h 5fffh 6000h 6fffh 7000h 7fffh 0020h 007fh 0080h 07ffh 0800h 0fffh 1000h callf !faddr instruction entry address br !addr instruction branch address call !addr instruction branch address branch/call address by geti brcb !caddr instruction branch address brcb !caddr instruction branch address brcb !caddr instruction branch address 765 0 brcb !caddr instruction branch address brcb !caddr instruction branch address brcb !caddr instruction branch address brcb !caddr instruction branch address brcb !caddr instruction branch address branch addresses for the following instructions ?br bcde ?br bcxa ?bra !addr1 ?calla !addr1 br $addr1 instruction relative branch address (?5 to ?, +2 to +16) m pd75p3018a 19 data sheet u11917ej2v0ds00 6.3 data memory (ram) ... 1024 4 bits figure 6-4 shows the data memory configuration. data memory consists of a data area and a peripheral hardware area. the data area consists of 1024 4-bit static ram. figure 6-4. data memory map note memory bank 0, 1, 2, or 3 can be selected as the stack area. (32 4) 256 4 (224 4) 256 4 (224 4) (32 4) 256 4 256 4 128 4 0 1 2 3 15 000h 01fh 020h 0ffh 100h 1dfh 1e0h 1ffh 200h 2ffh 300h 3ffh f80h fffh general-purpose register area display data memory data area static ram (1024 4) stack area note peripheral hardware area data memory memory bank not incorporated m pd75p3018a 20 data sheet u11917ej2v0ds00 7. instruction set (1) representation and coding formats for operands in the instructions operand area, use the following coding format to describe operands corresponding to the instructions operand representations (for further description, see the ra75x assembler package users manual language (u12385e) ). when there are several codes, select and use just one. codes that consist of uppercase letters and + or C symbols are key words that should be entered as they are. for immediate data, enter an appropriate numerical value or label. enter register flag symbols as label descriptors instead of mem, fmem, pmem, bit, etc. (for details, refer to the m pd753017 users manual (u11282e) ). the number of labels that can be entered for fmem and pmem are restricted. representation coding format reg x, a, b, c, d, e, h, l reg1 x, b, c, d, e, h, l rp xa, bc, de, hl rp1 bc, de, hl rp2 bc, de rp xa, bc, de, hl, xa, bc, de, hl rp1 bc, de, hl, xa, bc, de, hl rpa hl, hl+, hlC, de, dl rpa1 de, dl n4 4-bit immediate data or label n8 8-bit immediate data or label mem 8-bit immediate data or label note bit 2-bit immediate data or label fmem fb0h-fbfh, ff0h-fffh immediate data or label pmem fc0h-fffh immediate data or label addr 0000h-3fffh immediate data or label addr1 0000h-7fffh immediate data or label (mk ii mode only) caddr 12-bit immediate data or label faddr 11-bit immediate data or label taddr 20h-7fh immediate data (however, bit0 = 0) or label portn port0-port7 iexxx iebt, iecsi, iet0, iet1, iet2, ie0-ie2, ie4, iew rbn rb0-rb3 mbn mb0-mb3, mb15 note when processing 8-bit data, only even-numbered addresses can be specified. m pd75p3018a 21 data sheet u11917ej2v0ds00 (2) operation legend a : a register; 4-bit accumulator b : b register c : c register d : d register e : e register h : h register l : l register x : x register xa : register pair (xa); 8-bit accumulator bc : register pair (bc) de : register pair (de) hl : register pair (hl) xa : expansion register pair (xa) bc : expansion register pair (bc) de : expansion register pair (de) hl : expansion register pair (hl) pc : program counter sp : stack pointer cy : carry flag; bit accumulator psw : program status word mbe : memory bank enable flag rbe : register bank enable flag portn : port n (n = 0 to 7) ime : interrupt master enable flag ips : interrupt priority selection register iexxx : interrupt enable flag rbs : register bank selection register mbs : memory bank selection register pcc : processor clock control register . : delimiter for address and bit (xx) : addressed data xxh : hexadecimal data m pd75p3018a 22 data sheet u11917ej2v0ds00 (3) description of symbols used in addressing area remarks 1. mb indicates access-enabled memory banks. 2. in area *2, mb = 0 for both mbe and mbs. 3. in areas *4 and *5, mb = 15 for both mbe and mbs. 4. areas *6 to *11 indicate corresponding address-enabled areas. mb = 0 (000h-07fh) mb = 15 (f80h-fffh) mb = mbs mbs = 0-3, 15 mb = mbe ?mbs mbs = 0-3, 15 *1 mb = 0 *2 mbe = 1 : mbe = 0 : *3 mb = 15, fmem = fb0h-fbfh, ff0h-fffh mb = 15, pmem = fc0h-fffh addr = 0000h-3fffh *4 *5 *6 addr, addr1 = *7 (current pc) ?5 to (current pc) ? (current pc) +2 to (current pc) +16 *8 caddr = 0000h-0fffh (pc 14 , 13 , 12 = 000b) or 1000h-1fffh (pc 14 , 13 , 12 = 001b) or 2000h-2fffh (pc 14 , 13 , 12 = 010b) or 3000h-3fffh (pc 14 , 13 , 12 = 011b) or 4000h-4fffh (pc 14 , 13 , 12 = 100b: mk ii mode only) or 5000h-5fffh (pc 14 , 13 , 12 = 101b: mk ii mode only) or 6000h-6fffh (pc 14 , 13 , 12 = 110b: mk ii mode only) or 7000h-7f7fh (pc 14 , 13 , 12 = 111b: mk ii mode only) faddr = 0000h-07ffh taddr = 0020h-007fh addr1 = 0000h-7fffh (mk ii mode only) *9 *10 *11 program memory addressing data memory addressing m pd75p3018a 23 data sheet u11917ej2v0ds00 (4) description of machine cycles s indicates the number of machine cycles required for skipping of skip-specified instructions. the value of s varies as shown below. ? no skip ..................................................................... s = 0 ? skipped instruction is 1-byte or 2-byte instruction .... s = 1 ? skipped instruction is 3-byte instruction note .............. s = 2 note 3-byte instructions: br !addr, bra !addr1, call !addr, calla !addr1 caution the geti instruction is skipped for one machine cycle. one machine cycle equals one cycle (= t cy ) of the cpu clock f . use the pcc setting to select among four cycle times. m pd75p3018a 24 data sheet u11917ej2v0ds00 instruction mnemonic operand no. of machine operation addressing skip group bytes cycle area condition transfer mov a, #n4 1 1 a ? n4 string-effect a reg1, #n4 2 2 reg1 ? n4 xa, #n8 2 2 xa ? n8 string-effect a hl, #n8 2 2 hl ? n8 string-effect b rp2, #n8 2 2 rp2 ? n8 a, @hl 1 1 a ? (hl) *1 a, @hl+ 1 2+s a ? (hl), then l ? l+1 *1 l=0 a, @hlC 1 2+s a ? (hl), then l ? lC1 *1 l=fh a, @rpa1 1 1 a ? (rpa1) *2 xa, @hl 2 2 xa ? (hl) *1 @hl, a 1 1 (hl) ? a*1 @hl, xa 2 2 (hl) ? xa *1 a, mem 2 2 a ? (mem) *3 xa, mem 2 2 xa ? (mem) *3 mem, a 2 2 (mem) ? a*3 mem, xa 2 2 (mem) ? xa *3 a, reg 2 2 a ? reg xa, rp 2 2 xa ? rp reg1, a 2 2 reg1 ? a rp1, xa 2 2 rp1 ? xa xch a, @hl 1 1 a ? (hl) *1 a, @hl+ 1 2+s a ? (hl), then l ? l+1 *1 l=0 a, @hlC 1 2+s a ? (hl), then l ? lC1 *1 l=fh a, @rpa1 1 1 a ? (rpa1) *2 xa, @hl 2 2 xa ? (hl) *1 a, mem 2 2 a ? (mem) *3 xa, mem 2 2 xa ? (mem) *3 a, reg1 1 1 a ? reg1 xa, rp 2 2 xa ? rp table movt note 1 xa, @pcde 1 3 xa ? (pc 13-8 +de) rom reference xa ? (pc 14-8 +de) rom xa, @pcxa 1 3 xa ? (pc 13-8 +xa) rom xa ? (pc 14-8 +xa) rom xa, @bcde 1 3 xa ? (bcde) rom note 2 *6 xa ? (bcde) rom note 2 *11 xa, @bcxa 1 3 xa ? (bcxa) rom note 2 *6 xa ? (bcxa) rom note 2 *11 notes 1. shaded areas indicate support for mk ii mode only. other areas indicate support for mk i mode only. 2. only the low-order 3 bits in the b register are valid. m pd75p3018a 25 data sheet u11917ej2v0ds00 instruction mnemonic operand no. of machine operation addressing skip group bytes cycle area condition bit transfer mov1 cy, fmem.bit 2 2 cy ? (fmem.bit) *4 cy, pmem.@l 2 2 cy ? (pmem 7-2 +l 3-2 .bit(l 1-0 )) *5 cy, @h+mem.bit 2 2 cy ? (h+mem 3-0 .bit) *1 fmem.bit, cy 2 2 (fmem.bit) ? cy *4 pmem.@l, cy 2 2 (pmem 7-2 +l 3-2 .bit(l 1-0 )) ? cy *5 @h+mem.bit, cy 2 2 (h+mem 3-0 .bit) ? cy *1 arithmetic adds a, #n4 1 1+s a ? a+n4 carry xa, #n8 2 2+s xa ? xa+n8 carry a, @hl 1 1+s a ? a+(hl) *1 carry xa, rp 2 2+s xa ? xa+rp carry rp1, xa 2 2+s rp1 ? rp1+xa carry addc a, @hl 1 1 a, cy ? a+(hl)+cy *1 xa, rp 2 2 xa, cy ? xa+rp+cy rp1, xa 2 2 rp1, cy ? rp1+xa+cy subs a, @hl 1 1+s a ? aC(hl) *1 borrow xa, rp 2 2+s xa ? xaCrp borrow rp1, xa 2 2+s rp1 ? rp1Cxa borrow subc a, @hl 1 1 a, cy ? aC(hl)Ccy *1 xa, rp 2 2 xa, cy ? xaCrpCcy rp1, xa 2 2 rp1, cy ? rp1CxaCcy and a, #n4 2 2 a ? a n4 a, @hl 1 1 a ? a (hl) *1 xa, rp 2 2 xa ? xa rp rp1, xa 2 2 rp1 ? rp1 xa or a, #n4 2 2 a ? a n4 a, @hl 1 1 a ? a (hl) *1 xa, rp 2 2 xa ? xa rp rp1, xa 2 2 rp1 ? rp1 xa xor a, #n4 2 2 a ? a n4 a, @hl 1 1 a ? a (hl) *1 xa, rp 2 2 xa ? xa rp rp1, xa 2 2 rp1 ? rp1 xa accumulator rorc a 1 1 cy ? a 0 , a 3 ? cy, a n-1 ? a n manipulation not a 2 2 a ? a increment/ incs reg 1 1+s reg ? reg+1 reg=0 decrement rp1 1 1+s rp1 ? rp1+1 rp1=00h @hl 2 2+s (hl) ? (hl)+1 *1 (hl)=0 mem 2 2+s (mem) ? (mem)+1 *3 (mem)=0 decs reg 1 1+s reg ? regC1 reg=fh rp 2 2+s rp ? rpC1 rp=ffh m pd75p3018a 26 data sheet u11917ej2v0ds00 instruction mnemonic operand no. of machine operation addressing skip group bytes cycle area condition comparison ske reg, #n4 2 2+s skip if reg=n4 reg=n4 @hl, #n4 2 2+s skip if (hl)=n4 *1 (hl)=n4 a, @hl 1 1+s skip if a=(hl) *1 a=(hl) xa, @hl 2 2+s skip if xa=(hl) *1 xa=(hl) a, reg 2 2+s skip if a=reg a=reg xa, rp 2 2+s skip if xa=rp xa=rp carry flag set1 cy 1 1 cy ? 1 manipulation clr1 cy 1 1 cy ? 0 skt cy 1 1+s skip if cy=1 cy=1 not1 cy 1 1 cy ? cy memory bit set1 mem.bit 2 2 (mem.bit) ? 1*3 manipulation fmem.bit 2 2 (fmem.bit) 1 *4 pmem.@l 2 2 (pmem 7-2 +l 3-2 .bit(l 1-0 )) 1*5 @h+mem.bit 2 2 (h+mem 3-0 .bit) 1*1 clr1 mem.bit 2 2 (mem.bit) 0*3 fmem.bit 2 2 (fmem.bit) 0*4 pmem.@l 2 2 (pmem 7-2 +l 3-2 .bit(l 1-0 )) 0*5 @h+mem.bit 2 2 (h+mem 3-0 .bit) 0*1 skt mem.bit 2 2+s skip if(mem.bit)=1 *3 (mem.bit)=1 fmem.bit 2 2+s skip if(fmem.bit)=1 *4 (fmem.bit)=1 pmem.@l 2 2+s skip if(pmem 7-2 +l 3-2 .bit(l 1-0 ))=1 *5 (pmem.@l)=1 @h+mem.bit 2 2+s skip if(h+mem 3-0 .bit)=1 *1 (@h+mem.bit)=1 skf mem.bit 2 2+s skip if(mem.bit)=0 *3 (mem.bit)=0 fmem.bit 2 2+s skip if(fmem.bit)=0 *4 (fmem.bit)=0 pmem.@l 2 2+s skip if(pmem 7-2 +l 3-2 .bit(l 1-0 ))=0 *5 (pmem.@l)=0 @h+mem.bit 2 2+s skip if(h+mem 3-0 .bit)=0 *1 (@h+mem.bit)=0 sktclr fmem.bit 2 2+s skip if(fmem.bit)=1 and clear *4 (fmem.bit)=1 pmem.@l 2 2+s skip if(pmem 7-2 +l 3-2 .bit (l 1-0 ))=1 and clear *5 (pmem.@l)=1 @h+mem.bit 2 2+s skip if(h+mem 3-0 .bit)=1 and clear *1 (@h+mem.bit)=1 and1 cy, fmem.bit 2 2 cy ? cy (fmem.bit) *4 cy, pmem.@l 2 2 cy ? cy (pmem 7-2 +l 3-2 .bit(l 1-0 )) *5 cy, @h+mem.bit 2 2 cy ? c (h+mem 3-0 .bit) *1 or1 cy, fmem.bit 2 2 cy ? cy (fmem.bit) *4 cy, pmem.@l 2 2 cy ? cy (pmem 7-2 +l 3-2 .bit(l 1-0 )) *5 cy, @h+mem.bit 2 2 cy ? cy (h+mem 3-0 .bit) *1 xor1 cy, fmem.bit 2 2 cy ? cy (fmem.bit) *4 cy, pmem.@l 2 2 cy ? cy (pmem 7-2 +l 3-2 .bit(l 1-0 )) *5 cy, @h+mem.bit 2 2 cy ? c (h+mem 3-0 .bit) *1 ? ? ? ? ? ? ? m pd75p3018a 27 data sheet u11917ej2v0ds00 instruction mnemonic operand no. of machine operation addressing skip group bytes cycle area condition branch br note 1 addr pc 14 ? 0, pc 13-0 ? addr *6 use the assembler to select the most appropriate instruction among the following. ? br !addr ? brcb !caddr ? br $addr addr1 pc 14-0 ? addr1 *11 use the assembler to select the most appropriate instruction among the following. ? bra !addr1 ? br !addr ? brcb !caddr ? br $addr1 !addr 3 3 pc 14 ? 0, pc 13-0 ? addr *6 $addr 1 2 pc 14 ? 0, pc 13-0 ? addr *7 $addr1 1 2 pc 14-0 ? addr1 pcde 2 3 pc 14 ? 0, pc 13-0 ? pc 13-8 +de pc 14-0 ? pc 14-8 +de pcxa 2 3 pc 14 ? 0, pc 13-0 ? pc 13-8 +xa pc 14-0 ? pc 14-8 +xa bcde 2 3 pc 14 ? 0, pc 13-0 ? bcde note 2 *6 pc 14-0 ? bcde note 2 *11 bcxa 2 3 pc 14 ? 0, pc 13-0 ? bcxa note 2 *6 pc 14-0 ? bcxa note 2 *11 bra note 1 !addr 3 3 pc 14 ? 0, pc 13-0 ? addr *6 33pc 14-0 ? addr1 *11 brcb note 1 !caddr 2 2 pc 14 ? 0, pc 13-0 ? pc 13, 12 +caddr 11-0 *8 pc 14-0 ? pc 14, 13, 12 +caddr 11-0 notes 1. shaded areas indicate support for mk ii mode only. other areas indicate support for mk i mode only. 2. the only following bits are valid in the b register. for mk i mode : low-order 2 bits for mk ii mode : low-order 3 bits m pd75p3018a 28 data sheet u11917ej2v0ds00 instruction mnemonic operand no. of machine operation addressing skip group bytes cycle area condition subroutine calla note !addr1 3 3 (spC5) ? 0, pc 14-12 *11 stack control (spC6)(spC3)(spC4) ? pc 11-0 (spC2) ? x, x, mbe, rbe pc 14C0 ? addr1, sp ? spC6 call note !addr 3 3 (spC4)(spC1)(spC2) ? pc 11-0 *6 (spC3) ? mbe, rbe, pc 13, 12 pc 14 ? 0, pc 13C0 ? addr, sp ? spC4 4 (spC5) ? 0, pc 14-12 (spC6)(spC3)(spC4) ? pc 11-0 (spC2) ? x, x, mbe, rbe pc 14 ? 0, pc 13-0 ? addr, sp ? spC6 callf note !faddr 2 2 (spC4)(spC1)(spC2) ? pc 11-0 *9 (spC3) ? mbe, rbe, pc 13, 12 pc 14 ? 0, pc 13-0 ? 000+faddr, sp ? spC4 3 (spC5) ? 0, pc 14-12 (spC6)(spC3)(spC4) ? pc 11-0 (spC2) ? x, x, mbe, rbe pc 14-0 ? 0000+faddr, sp ? spC6 ret note 1 3 mbe, rbe, pc 13, 12 ? (sp+1) pc 11-0 ? (sp)(sp+3)(sp+2) pc 14 ? 0, sp ? sp+4 x, x, mbe, rbe ? (sp+4) 0, pc 14-12 ? (sp+1) pc 11-0 ? (sp)(sp+3)(sp+2) sp ? sp+6 rets note 1 3+s mbe, rbe, pc 13, 12 ? (sp+1) unconditional pc 11-0 ? (sp)(sp+3)(sp+2) pc 14 ? 0, sp ? sp+4 then skip unconditionally x, x, mbe, rbe ? (sp+4) 0, pc 14-12 ? (sp+1) pc 11-0 ? (sp)(sp+3)(sp+2) sp ? sp+6 then skip unconditionally reti note 13 mbe, rbe, pc 13, 12 ? (sp+1), pc 14 ? 0 pc 11-0 ? (sp)(sp+3)(sp+2) psw ? (sp+4)(sp+5), sp ? sp+6 0, pc 14-12 ? (sp+1) pc 11-0 ? (sp)(sp+3)(sp+2) psw ? (sp+4)(sp+5), sp ? sp+6 note shaded areas indicate support for mk ii mode only. other areas indicate support for mk i mode only. m pd75p3018a 29 data sheet u11917ej2v0ds00 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - instruction mnemonic operand no. of machine operation addressing skip group bytes cycle area condition subroutine push rp 1 1 (spC1)(spC2) ? rp, sp ? spC2 stack control bs 2 2 (spC1) ? mbs, (spC2) ? rbs, sp ? spC2 pop rp 1 1 rp ? (sp+1)(sp), sp ? sp+2 bs 2 2 mbs ? (sp+1), rbs ? (sp), sp ? sp+2 interrupt ei 2 2 ime(ips.3) ? 1 control iexxx 2 2 iexxx ? 1 di 2 2 ime(ips.3) ? 0 iexxx 2 2 iexxx ? 0 i/o in note 1 a, portn 2 2 a ? portn (n=0-7) xa, portn 2 2 xa ? portn+ 1 , portn (n=4, 6) out note 1 portn, a 2 2 portn ? a (n=2-7) portn, xa 2 2 portn+ 1 , portn ? xa (n=4, 6) cpu control halt 2 2 set halt mode(pcc.2 ? 1) stop 2 2 set stop mode(pcc.3 ? 1) nop 1 1 no operation special sel rbn 2 2 rbs ? n (n=0-3) mbn 2 2 mbs ? n (n=0-3, 15) geti note 2, 3 taddr 1 3 ? when using tbr instruction *10 pc 13-0 ? (taddr) 5-0 +(taddr+1), pc 14 ? 0 ? when using tcall instruction (spC4)(spC1)(spC2) ? pc 11-0 (spC3) ? mbe, rbe, pc 13, 12 , pc 14 ? 0 pc 13-0 ? (taddr) 5-0 +(taddr+1) sp ? spC4 ? when using instruction other than determined by tbr or tcall referenced execute (taddr)(taddr+1) instructions instruction 1 3 ? when using tbr instruction *10 pc 13-0 ? (taddr) 5-0 +(taddr+1), pc 14 ? 0 4 ? when using tcall instruction (spC5) ? 0, pc 14-12 (spC6)(spC3)(spC4) ? pc 11-0 (spC2) ? x, x, mbe, rbe, pc 14 ? 0 pc 13-0 ? (taddr) 5-0 +(taddr+1) sp ? spC6 3 ? when using instruction other than determined by tbr or tcall referenced execute (taddr)(taddr+1) instructions instruction notes 1. before executing the in or out instruction, set mbe to 0 or 1 and set mbs to 15. 2. tbr and tcall instructions are assembler pseudo-instructions for the geti instructions table definitions. 3. shaded areas indicate support for mk ii mode only. other areas indicate support for mk i mode only. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - m pd75p3018a 30 data sheet u11917ej2v0ds00 8. one-time prom (program memory) write and verify the program memory contained in the m pd75p3018a is a 32768 8-bit one-time prom that can be electrically written one time only. the pins listed in the table below are used for this one-time proms write/verify operations. clock input from the x1 pin is used instead of address input as a method for updating addresses. pin function v pp pin where program voltage is applied during program memory write/verify (usually v dd potential) x1, x2 clock input pins for address updating during program memory write/verify. input the x1 pins inverted signal to the x2 pin. md0-md3 operation mode selection pin for program memory write/verify d0/p40 to d3/p43 8-bit data i/o pins for program memory write/verify (low-order 4 bits) d4/p50 to d7/p53 (high-order 4 bits) v dd pin where power supply voltage is applied. applies v dd = 1.8 to 5.5 v in normal operation mode and +6 v for program memory write/verify. caution pins not used for program memory write/verify should be connected to v ss via a resistor individually. 8.1 operation modes for program memory write/verify when +6 v is applied to the v dd pin and +12.5 v to the v pp pin, the m pd75p3018a enters the program memory write/verify mode. the following operation modes can be specified by setting pins md0 to md3 as shown below. operation mode specification operation mode v pp v dd md0 md1 md2 md3 +12.5 v +6 v h l h l zero-clear program memory address l h h h write mode l l h h verify mode h x h h program inhibit mode x: l or h m pd75p3018a 31 data sheet u11917ej2v0ds00 8.2 program memory write procedure program memory can be written at high speed using the following procedure. (1) pull unused pins to vss through resistors. set the x1 pin low. (2) supply 5 v to the v dd and v pp pins. (3) wait 10 m s. (4) select the zero-clear program memory address mode. (5) supply 6 v to the v dd and 12.5 v to the v pp pins. (6) write data in the 1 ms write mode. (7) select the verify mode. if the data is correct, go to step (8) and if not, repeat steps (6) and (7). (8) (x : number of write operations from steps (6) and (7)) 1 ms additional write. (9) apply four pulses to the x1 pin to increment the program memory address by one. (10) repeat steps (6) to (9) until the end address is reached. (11) select the zero-clear program memory address mode. (12) return the v dd and v pp pins back to 5 v. (13) turn off the power. the following figure shows steps (2) to (9). v pp v dd v dd + 1 v dd v pp v dd x1 d0/p40 to d3/p43 d4/p50 to d7/p53 md0/p30 md1/p31 md2/p32 md3/p33 x repetitions write verify additional write address increment data input data output data input m pd75p3018a 32 data sheet u11917ej2v0ds00 8.3 program memory read procedure the m pd75p3018a can read program memory contents using the following procedure. (1) pull unused pins to vss through resistors. set the x1 pin low. (2) supply 5 v to the v dd and v pp pins. (3) wait 10 m s. (4) select the zero-clear program memory address mode. (5) supply 6 v to the v dd and 12.5 v to the v pp pins. (6) select the verify mode. apply four pulses to the x1 pin. every four clock pulses will output the data stored in one address. (7) select the zero-clear program memory address mode. (8) return the v dd and v pp pins back to 5 v. (9) turn off the power. the following figure shows steps (2) to (7). v pp v dd v dd + 1 v dd v pp v dd x1 d0/p40 to d3/p43 d4/p50 to d7/p53 md0/p30 md2/p32 md3/p33 md1/p31 ? data output data output m pd75p3018a 33 data sheet u11917ej2v0ds00 8.4 one-time prom screening due to its structure, the one-time prom cannot be fully tested before shipment by nec. therefore, nec recommends that after the required data is written and the prom is stored under the temperature and time conditions shown below, the prom should be verified via a screening. storage temperature storage time 125 c 24 hours m pd75p3018a 34 data sheet u11917ej2v0ds00 9. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd C0.3 to +7.0 v prom supply voltage v pp C0.3 to +13.5 v input voltage v i1 other than ports 4 and 5 C0.3 to v dd + 0.3 v v i2 ports 4 and 5 (during n-ch open drain) C0.3 to +14 v output voltage v o C0.3 to v dd + 0.3 v high-level output current i oh per pin C10 ma total of all pins C30 ma low-level output current i ol per pin 30 ma total of all pins 220 ma operating ambient t a C40 to +85 note c temperature storage temperature t stg C65 to +150 c note to drive lcd in normal mode, t a = C10 to +85 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. capacitance (t a = 25 c, v dd = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c in f = 1 mhz 15 pf output capacitance c out unmeasured pins returned to 0 v 15 pf i/o capacitance c io 15 pf m pd75p3018a 35 data sheet u11917ej2v0ds00 main system clock oscillator characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit ceramic oscillation frequency 1.0 6.0 note 2 mhz resonator (f x ) note 1 oscillation after v dd has 4 ms stabilization time note 3 reached min. value of oscillation voltage range crystal oscillation frequency 1.0 6.0 note 2 mhz resonator (f x ) note 1 oscillation v dd = 4.5 to 5.5 v 10 ms stabilization time note 3 30 external x1 input frequency 1.0 6.0 note 2 mhz clock (f x ) note 1 x1 input high-/ 83.3 500 ns low-level width (t xh , t xl ) notes 1. the oscillation frequency and x1 input frequency shown above indicate characteristics of the oscillator only. for the instruction execution time, refer to ac characteristics . 2. if the oscillation frequency is 4.19 mhz < f x 6.0 mhz at 1.8 v v dd < 2.7 v, do not select processor clock control register (pcc) = 0011. if pcc = 0011, one machine cycle is less than 0.95 m s, falling short of the rated value of 0.95 m s. 3. the oscillation stabilization time is the time required for oscillation to be stabilized after v dd has been applied or stop mode has been released. caution when using the main system clock oscillator, wire the portion enclosed in the broken line in the above figure as follows to prevent adverse influence due to wiring capacitance: ? keep the wiring length as short as possible. ? do not cross the wiring with other signal lines. ? do not route the wiring in the vicinity of a line through which a high alternating current flows. ? always keep the ground point of the capacitor of the oscillator at the same potential as v dd . ? do not ground to a power supply pattern through which a high current flows. ? do not extract signals from the oscillator. remark for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. x1 x2 c1 c2 v dd x1 x2 c1 c2 v dd x1 x2 m pd75p3018a 36 data sheet u11917ej2v0ds00 subsystem clock oscillator characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit crystal oscillation frequency 32 32.768 35 khz resonator (f xt ) note 1 oscillation v dd = 4.5 to 5.5 v 1.0 2 s stabilization time note 2 10 external xt1 input frequency 32 100 khz clock (f xt ) note 1 xt1 input high-/ 5 15 m s low-level width (t xth , t xtl ) notes 1. the oscillation frequency and xt1 input frequency shown above indicate characteristics of the oscillator only. for the instruction execution time, refer to ac characteristics . 2. the oscillation stabilization time is the time required for oscillation to be stabilized after v dd has been applied. caution when using the subsystem clock oscillator , wire the portion enclosed in the broken line in the above figure as follows to prevent adverse influence due to wiring capacitance: ? keep the wiring length as short as possible. ? do not cross the wiring with other signal lines. ? do not route the wiring in the vicinity of a line through which a high alternating current flows. ? always keep the ground point of the capacitor of the oscillator at the same potential as v dd . ? do not ground to a power supply pattern through which a high current flows. ? do not extract signals from the oscillator. the subsystem clock oscillator has a low amplification factor to reduce current consumption and is more susceptible to noise than the main system clock oscillator. therefore, exercise utmost care in wiring the subsystem clock oscillator. remark for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. xt1 xt2 c3 c4 r v dd xt1 xt2 m pd75p3018a 37 data sheet u11917ej2v0ds00 dc characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit low-level output i ol per pin 15 ma current total of all pins 150 ma high-level input v ih1 ports 2, 3 2.7 v v dd 5.5 v 0.7v dd v dd v voltage 1.8 v v dd < 2.7 v 0.9v dd v dd v v ih2 ports 0, 1, 6, 7, reset 2.7 v v dd 5.5 v 0.8v dd v dd v 1.8 v v dd < 2.7 v 0.9v dd v dd v v ih3 ports 4, 5 2.7 v v dd 5.5 v 0.7v dd 13 v (n-ch open-drain) 1.8 v v dd < 2.7 v 0.9v dd 13 v v ih4 x1, xt1 v dd C 0.1 v dd v low-level input v il1 ports 2 to 5 2.7 v v dd 5.5 v 0 0.3v dd v voltage 1.8 v v dd < 2.7 v 0 0.1v dd v v il2 ports 0, 1, 6, 7, reset 2.7 v v dd 5.5 v 0 0.2v dd v 1.8 v v dd < 2.7 v 0 0.1v dd v v il3 x1, xt1 0 0.1 v high-level output v oh sck, so, ports 2, 3, 6, 7, bp0 to bp7 v dd C 0.5 v voltage i oh = C1.0 ma low-level output v ol1 sck, so, ports 2 to 7, i ol = 15 ma 0.2 2.0 v voltage bp0 to bp7 v dd = 4.5 to 5.5 v i ol = 1.6 ma 0.4 v v ol2 sb0, sb1 n-ch open-drain 0.2v dd v pull-up resistor 3 1 k w high-level input i lih1 v in = v dd pins other than x1, xt1 3 m a leakage current i lih2 x1, xt1 20 m a i lih3 v in = 13 v ports 4, 5 (n-ch open-drain) 20 m a low-level input i lil1 v in = 0 v pins other than x1, xt1, ports 4, 5 C3 m a leakage current i lil2 x1, xt1 C20 m a i lil3 ports 4, 5 (n-ch open-drain) C3 m a when input instruction is not executed ports 4, 5 (n-ch open- C30 m a drain). when input v dd = 5.0 v C10 C27 m a instruction is executed v dd = 3.0 v C3 C8 m a high-level output i loh1 v out = v dd sck, so/sb0, sb1, ports 2, 3, 6, 7 3 m a leakage current i loh2 v out = 13 v ports 4, 5 (n-ch open-drain) 20 m a low-level output i lol v out = 0 v C3 m a leakage current internal pull-up r l v in = 0 v ports 0 to 3, 6, 7 (except p00 pin) 50 100 200 k w resistor m pd75p3018a 38 data sheet u11917ej2v0ds00 v dd = 3.0 v 10% 3.5 12 m a v dd = 3.0 v, t a = 25 c 3.5 7 m a v dd = 3.0 v 10% 39 117 m a v dd = 3.0 v, t a = 25 c3978 m a dc characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit lcd drive voltage v lcd vac0 = 0 t a = C40 to +85 c 2.7 v dd v t a = C10 to +85 c 2.2 v dd v vac0 = 1 1.8 v dd v vac current note 1 i vac vac0 = 1, v dd = 2.0 v 10% 1 4 m a lcd output voltage v odc i o = 1.0 m av lcd0 = v lcd 0 0.2 v deviation note 2 v lcd1 = v lcd 2/3 (common) v lcd2 = v lcd 1/3 lcd output voltage v ods i o = 0.5 m a 1.8 v v lcd v dd 0 0.2 v deviation note 2 (segment) supply current note 3 i dd1 6.0 mhz note 4 v dd = 5.0 v 10% note 5 3.7 11.0 ma crystal v dd = 3.0 v 10% note 6 0.73 2.2 ma i dd2 oscillation halt v dd = 5.0 v 10% 0.92 2.6 ma c1 = c2 = 22 pf mode v dd = 3.0 v 10% 0.3 0.9 ma i dd1 4.19 mhz note 4 v dd = 5.0 v 10% note 5 2.7 8.0 ma crystal v dd = 3.0 v 10% note 6 0.57 1.7 ma i dd2 oscillation halt v dd = 5.0 v 10% 0.90 2.5 ma c1 = c2 = 22 pf mode v dd = 3.0 v 10% 0.28 0.8 ma i dd3 32.768 low- v dd = 3.0 v 10% 42 126 m a khz note 7 voltage v dd = 2.0 v 10% 37 110 m a crystal mode note 8 v dd = 3.0 v, t a = 25 c4284 m a oscillation i dd4 halt low- v dd = 3.0 v 10% 8.5 25 m a mode voltage v dd = 2.0 v 10% 5.8 17 m a mode note 8 v dd = 3.0 v, t a = 25 c 8.5 17 m a i dd5 xt1 = 0 v note 10 v dd = 5.0 v 10% 0.05 10 m a stop mode v dd = 3.0 v 10% 0.02 5 m a t a = 25 c 0.02 3 m a notes 1. clear vac0 to 0 in the low current consumption mode and stop mode. when vac0 is set to 1, the current increases by about 1 m a. 2. voltage deviation is the difference between the ideal values (vlcdn ; n = 0, 1, 2) of the segment and common outputs and the output voltage. 3. the current flowing through the internal pull-up resistor is not included. 4. including the case when the subsystem clock oscillates. 5. when the device operates in high-speed mode with the processor clock control register (pcc) set to 0011. 6. when the device operates in low-speed mode with pcc set to 0000. 7. when the device operates on the subsystem clock, with the system clock control register (scc) set to 1001 and oscillation of the main system clock stopped. 8. when the sub-oscillation circuit control register (sos) is set to 0000. 9. when the sos is set to 0010. 10. when the sos is set to 00x1, and the feedback resistor of the sub-oscillator is cut (x: dont care). low current consump- tion mode note 9 low current consump- tion mode note 9 m pd75p3018a 39 data sheet u11917ej2v0ds00 ac characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit cpu clock cycle time note 1 t cy operation with v dd = 2.7 to 5.5 v 0.67 64 m s (minimum instruction execution main system clock 0.95 64 m s time = 1 machine cycle) operation with subsystem clock 114 122 125 m s ti0, ti1, ti2 input frequency f ti v dd = 2.7 to 5.5 v 0 1.0 mhz 0 275 khz ti0, ti1, ti2 input high-/ t tih , t til v dd = 2.7 to 5.5 v 0.48 m s low-level width 1.8 m s interrupt input high-/low-level t inth , t intl int0 im02 = 0 note 2 m s width im02 = 1 10 m s int1, 2, 4 10 m s kr0-7 10 m s reset low-level width t rsl 10 m s notes 1. the cycle time (minimum instruc- tion execution time) of the cpu clock ( f ) is determined by the oscillation frequency of the connected resonator (and external clock), the system clock control register (scc), and processor clock control register (pcc). the figure on the right shows the supply voltage v dd vs. cycle time t cy characteristics when the device operates with the main system clock. 2. 2t cy or 128/f x depending on the setting of the interrupt mode register (im0). operation guaranteed range supply voltage v dd [v] 0123456 0.5 1 2 3 4 5 6 60 64 cycle time t cy [ s] t cy vs v dd (with main system clock) m pd75p3018a 40 data sheet u11917ej2v0ds00 serial transfer operation 2-wire and 3-wire serial i/o modes (sck ... internal clock output): (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit sck cycle time t kcy1 v dd = 2.7 to 5.5 v 1300 ns 3800 ns sck high-/low-level width t kl1 , t kh1 v dd = 2.7 to 5.5 v t kcy1 /2C50 ns t kcy1 /2C150 ns si note 1 setup time (to sck - ) t sik1 v dd = 2.7 to 5.5 v 150 ns 500 ns si note 1 hold time (from sck - ) t ksi1 v dd = 2.7 to 5.5 v 400 ns 600 ns sck ? so note 1 output t kso1 r l = 1 k w , note 2 v dd = 2.7 to 5.5 v 0 250 ns delay time c l = 100 pf 0 1000 ns notes 1. in 2-wire serial i/o mode, read sb0 or sb1 instead. 2. r l and c l respectively indicate the load resistance and load capacitance of the so output line. 2-wire and 3-wire serial i/o modes (sck ... external clock input): (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit sck cycle time t kcy2 v dd = 2.7 to 5.5 v 800 ns 3200 ns sck high-/low-level width t kl2 , t kh2 v dd = 2.7 to 5.5 v 400 ns 1600 ns si note 1 setup time (to sck - ) t sik2 v dd = 2.7 to 5.5 v 100 ns 150 ns si note 1 hold time (from sck - ) t ksi2 v dd = 2.7 to 5.5 v 400 ns 600 ns sck ? so note 1 output t kso2 r l = 1 k w , note 2 v dd = 2.7 to 5.5 v 0 300 ns delay time c l = 100 pf 0 1000 ns notes 1. in 2-wire serial i/o mode, read sb0 or sb1 instead. 2. r l and c l respectively indicate the load resistance and load capacitance of the so output line. m pd75p3018a 41 data sheet u11917ej2v0ds00 sbi mode (sck ... internal clock output (master)): (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit sck cycle time t kcy3 v dd = 2.7 to 5.5 v 1300 ns 3800 ns sck high-/low-level width t kl3 , t kh3 v dd = 2.7 to 5.5 v t kcy3 /2C50 ns t kcy3 /2C150 ns sb0, 1 setup time t sik3 v dd = 2.7 to 5.5 v 150 ns (to sck - ) 500 ns sb0, 1 hold time (from sck - ) t ksi3 t kcy3 /2 ns sck ? sb0, 1 output t kso3 r l = 1 k w , note v dd = 2.7 to 5.5 v 0 250 ns delay time c l = 100 pf 0 1000 ns sck - ? sb0, 1 t ksb t kcy3 ns sb0, 1 ? sck t sbk t kcy3 ns sb0, 1 low-level width t sbl t kcy3 ns sb0, 1 high-level width t sbh t kcy3 ns note r l and c l respectively indicate the load resistance and load capacitance of the sb0, 1 output line. sbi mode (sck ... external clock input (slave)): (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit sck cycle time t kcy4 v dd = 2.7 to 5.5 v 800 ns 3200 ns sck high-/low-level width t kl4 , t kh4 v dd = 2.7 to 5.5 v 400 ns 1600 ns sb0, 1 setup time t sik4 v dd = 2.7 to 5.5 v 100 ns (to sck - ) 150 ns sb0, 1 hold time (from sck - ) t ksi4 t kcy4 /2 ns sck ? sb0, 1 output t kso4 r l = 1 k w , note v dd = 2.7 to 5.5 v 0 300 ns delay time c l = 100 pf 0 1000 ns sck - ? sb0, 1 t ksb t kcy4 ns sb0, 1 ? sck t sbk t kcy4 ns sb0, 1 low-level width t sbl t kcy4 ns sb0, 1 high-level width t sbh t kcy4 ns note r l and c l respectively indicate the load resistance and load capacitance of the sb0, 1 output line. m pd75p3018a 42 data sheet u11917ej2v0ds00 ac timing test points (except x1 and xt1 inputs) clock timing ti0, ti1, ti2 timing v ih (min.) v il (max.) v ih (min.) v il (max.) v oh (min.) v ol (max.) v oh (min.) v ol (max.) xt1 input 1/f xt t xtl t xth v dd ?.1 v 0.1 v x1 input 1/f x t xl t xh v dd ?.1 v 0.1 v ti0, ti1, ti2 1/f ti t til t tih m pd75p3018a 43 data sheet u11917ej2v0ds00 serial transfer timing 3-wire serial i/o mode 2-wire serial i/o mode sck t kcy1,2 t kl1,2 t kh1,2 t sik1,2 t ksi1,2 si t kso1,2 input data output data so sck t kcy1,2 t kl1,2 t kh1,2 t sik1,2 t ksi1,2 t kso1,2 sb0, 1 m pd75p3018a 44 data sheet u11917ej2v0ds00 serial transfer timing bus release signal transfer command signal transfer interrupt input timing reset input timing t ksb t sbl t sbh t sbk t kcy3, 4 t kl3, 4 t kh3, 4 t sik3, 4 t ksi3, 4 t kso3, 4 sck sb0, 1 t kcy3, 4 t kl3, 4 t kh3, 4 t ksb t sbk t sik3, 4 t kso3, 4 sb0, 1 sck t ksi3, 4 t intl t inth int0, 1, 2, 4 kr0-7 t rsl reset m pd75p3018a 45 data sheet u11917ej2v0ds00 data retention characteristics of data memory in stop mode and at low supply voltage (t a = C40 to +85 c) parameter symbol conditions min. typ. max. unit data retention power v dddr 1.8 5.5 v supply voltage release signal setup time t srel 0 m s oscillation stabilization t wait released by reset 2 15 /f x ms wait time note 1 released by interrupt request note 2 ms notes 1. the oscillation stabilization wait time is the time during which the cpu stops operating to prevent unstable operation when oscillation is started. 2. set by the basic interval timer mode register (btm). (refer to the table below.) wait time btm3 btm2 btm1 btm0 f x = 4.19 mhz f x = 6.0 mhz C0002 20 /f x (approx. 250 ms) 2 20 /f x (approx. 175 ms) C0112 17 /f x (approx. 31.3 ms) 2 17 /f x (approx. 21.8 ms) C1012 15 /f x (approx. 7.81 ms) 2 15 /f x (approx. 5.46 ms) C1112 13 /f x (approx. 1.95 ms) 2 13 /f x (approx. 1.37 ms) data retention timing (standby release signal: when stop mode released by interrupt signal) stop mode v dd operation mode internal reset operation halt mode data retention mode t srel t wait stop instruction execution reset v dddr stop mode v dd operation mode halt mode data retention mode t srel t wait stop instruction execution standby release signal (interrupt request) v dddr data retention timing (when stop mode released by reset) m pd75p3018a 46 data sheet u11917ej2v0ds00 dc programming characteristics (t a = 25 5 c, v dd = 6.0 0.25 v, v pp = 12.5 0.3 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit high-level input voltage v ih1 pins other than x1, x2 0.7v dd v dd v v ih2 x1, x2 v dd C 0.5 v dd v low-level input voltage v il1 pins other than x1, x2 0 0.3v dd v v il2 x1, x2 0 0.4 v input leakage current i li v in = v il or v ih 10 m a high-level output voltage v oh i oh = C1 ma v dd C 1.0 v low-level output voltage v ol i ol = 1.6 ma 0.4 v v dd supply current i dd 30 ma v pp supply current i pp md0 = v il , md1 = v ih 30 ma cautions 1. ensure that v pp does not exceed +13.5 v including overshoot. 2. v dd must be applied before v pp , and cut after v pp . ac programming characteristics (t a = 25 5 c, v dd = 6.0 0.25 v, v pp = 12.5 0.3 v, v ss = 0 v) parameter symbol note 1 conditions min. typ. max. unit address setup time note 2 (to md0 )t as t as 2 m s md1 setup time (to md0 )t m1s t oes 2 m s data setup time (to md0 )t ds t ds 2 m s address hold time note 2 (from md0 - )t ah t ah 2 m s data hold time (from md0 - )t dh t dh 2 m s md0 -? data output float delay time t df t df 0 130 ns v pp setup time (to md3 - )t vps t vps 2 m s v dd setup time (to md3 - )t vds t vcs 2 m s initial program pulse width t pw t pw 0.95 1.0 1.05 ms additional program pulse width t opw t opw 0.95 21.0 ms md0 setup time (to md1 - )t m0s t ces 2 m s md0 ? data output delay time t dv t dv md0 = md1 = v il 1 m s md1 hold time (from md0 - )t m1h t oeh t m1h + t m1r 3 50 m s2 m s md1 recovery time (from md0 )t m1r t or 2 m s program counter reset time t pcr 10 m s x1 input high-/low-level widths t xh , t xl 0.125 m s x1 input frequency f x 4.19 mhz initial mode setting time t i 2 m s md3 setup time (to md1 - )t m3s 2 m s md3 hold time (from md1 )t m3h 2 m s md3 setup time (to md0 )t m3sr program memory read 2 m s data output delay time from address note 2 t dad t acc program memory read 2 m s data output hold time from address note 2 t had t oh program memory read 0 130 m s md3 hold time (from md0 - )t m3hr program memory read 2 m s md3 ? data output float delay time t dfr program memory read 2 m s notes 1. symbol of corresponding m pd27c256a 2. the internal address signal is incremented by 1 on the 4th rise of the x1 input, and is not connected to a pin. m pd75p3018a 47 data sheet u11917ej2v0ds00 program memory write timing program memory read timing v pp v dd v dd +1 v dd x1 d0/p40-d3/p43 d4/p50-d7/p53 md0/p30 md1/p31 md2/p32 md3/p33 v pp v dd data input data output data input data input t vps t vds t xh t xl t i t ds t dh t pw t dv t df t m1r t m0s t ds t dh t opw t ah t as t m1s t m1h t pcr t m3s t m3h v pp v dd v dd +1 v dd x1 d0/p40-d3/p43 d4/p50-d7/p53 md0/p30 md1/p31 md2/p32 md3/p33 v dd v pp data output data output t vps t vds t xh t xl t dad t had t dv t dfr t m3hr t i t pcr t m3sr m pd75p3018a 48 data sheet u11917ej2v0ds00 10. package drawings 80-pin plastic qfp (14x14) note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.2 0.4 14.0 0.2 0.13 0.825 i 17.2 0.4 j c 14.0 0.2 h 0.30 0.10 0.65 (t.p.) k 1.6 0.2 l 0.8 0.2 f 0.825 s80gc-65-3b9-6 n p q 0.10 2.7 0.1 0.1 0.1 r s 5 5 3.0 max. m 0.15 + 0.10 - 0.05 60 61 40 80 1 21 20 41 s s n j detail of lead end c d a b r k m l p i s q g f m h m pd75p3018a 49 data sheet u11917ej2v0ds00 80-pin plastic qfp (14x14) note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.20 0.20 14.00 0.20 0.13 0.825 i 17.20 0.20 j c 14.00 0.20 h 0.32 0.06 0.65 (t.p.) k 1.60 0.20 p 1.40 0.10 q 0.125 0.075 l 0.80 0.20 f 0.825 n 0.10 m 0.17 + 0.03 - 0.07 p80gc-65-8bt-1 s 1.70 max. r3 + 7 - 3 41 60 40 61 21 80 20 1 s s n j detail of lead end c d a b r k m l p i s q g f m h m pd75p3018a 50 data sheet u11917ej2v0ds00 20 1 s 80 pin plastic tqfp (fine pitch) (12x12) item millimeters i j 0.50 (t.p.) 0.10 a 14.00 0.20 b 12.00 0.20 c 12.00 0.20 d 14.00 0.20 f g 1.25 1.25 h 0.22 p80gk-50-be9-6 s 1.27 max. k 1.00 0.20 l 0.50 0.20 m 0.145 n 0.10 p 1.05 0.07 q 0.10 0.05 r5 5 +0.05 ?.04 +0.055 ?.045 j ns l k m detail of lead end 61 60 41 40 21 80 a b c d s qr g f p hi m note each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. m pd75p3018a 51 data sheet u11917ej2v0ds00 80-pin plastic tqfp (fine pitch) (12x12) item millimeters g h 0.22 0.05 1.25 a 14.0 0.2 c 12.0 0.2 d f 1.25 14.0 0.2 b 12.0 0.2 m n 0.08 0.145 0.05 p q 0.1 0.05 1.0 j 0.5 (t.p.) k l 0.5 1.0 0.2 i 0.08 s 1.1 0.1 r 3 + 4 - 3 r h k l j f q g i t u s p detail of lead end note each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. 60 41 40 21 61 80 120 m s s cd a b n m p80gk-50-9eu-1 t 0.25 u 0.6 0.15 m pd75p3018a 52 data sheet u11917ej2v0ds00 11. recommended soldering conditions solder the m pd75p3018a under the following recommended conditions. for the details on the recommended soldering conditions, refer to information document semiconductor device mounting technology manual (c10535e) . for the soldering methods and conditions other than those recommended, consult nec. table 11-1. soldering conditions of surface mount type (1/2) (1) m pd75p3018agc-3b9: 80-pin plastic qfp (14 14 mm, resin thickness 2.7 mm) soldering method soldering conditions symbol infrared reflow package peak temperature: 235 c, reflow time: 30 seconds or below (210 c ir35-00-3 or higher), number of reflow processes: 3 max. vps package peak temperature: 215 c, reflow time: 40 seconds or below (200 c vp15-00-3 or higher), number of reflow processes: 3 max. wave soldering solder temperature: 260 c or below, flow time: 10 seconds or below, ws60-00-1 number of flow processes: 1 preheating temperature: 120 c or below (package surface temperature) partial heating pin temperature: 300 c or below, time: 3 seconds or below (per side of device) caution do not use two or more soldering methods in combination (except the partial heating method). (2) m pd75p3018agc-8bt: 80-pin plastic qfp (14 14 mm, resin thickness 1.4 mm) soldering method soldering conditions symbol infrared reflow package peak temperature: 235 c, reflow time: 30 seconds or below (210 c ir35-00-2 or higher), number of reflow processes: 2 max. vps package peak temperature: 215 c, reflow time: 40 seconds or below (200 c vp15-00-2 or higher), number of reflow processes: 2 max. wave soldering solder temperature: 260 c or below, flow time: 10 seconds or below, ws60-00-1 number of flow processes: 1 preheating temperature: 120 c or below (package surface temperature) partial heating pin temperature: 300 c or below, time: 3 seconds or below (per side of device) caution do not use two or more soldering methods in combination (except the partial heating method). m pd75p3018a 53 data sheet u11917ej2v0ds00 table 11-1. soldering conditions of surface mount type (2/2) (3) m pd75p3018agk-be9: 80-pin plastic tqfp (fine pitch) (12 12 mm, resin thickness 1.05 mm) soldering method soldering conditions symbol infrared reflow package peak temperature: 235 c, reflow time: 30 seconds or below (210 c ir35-107-3 or higher), number of reflow processes: 3 max., exposure limit: 7 days note (after that, prebaking is necessary at 125 c for 10 hours) vps package peak temperature: 215 c, reflow time: 40 seconds or below (200 c vp15-107-3 or higher), number of reflow processes: 3 max., exposure limit: 7 days note (after that, prebaking is necessary at 125 c for 10 hours) partial heating pin temperature: 300 c or below, time: 3 seconds or below (per side of device) note the number of days for storage after the dry pack has been opened. the storage conditions are 25 c, 65% rh max. caution do not use two or more soldering methods in combination (except the partial heating method). (4) m pd75p3018agk-9eu: 80-pin plastic tqfp (fine pitch) (12 12 mm, resin thickness 1.00 mm) soldering method soldering conditions symbol infrared reflow package peak temperature: 235 c, reflow time: 30 seconds or below (210 c ir35-107-2 or higher), number of reflow processes: 2 max., exposure limit: 7 days note (after that, prebaking is necessary at 125 c for 10 hours) vps package peak temperature: 215 c, reflow time: 40 seconds or below (200 c vp15-107-2 or higher), number of reflow processes: 2 max., exposure limit: 7 days note (after that, prebaking is necessary at 125 c for 10 hours) partial heating pin temperature: 300 c or below, time: 3 seconds or below (per side of device) note the number of days for storage after the dry pack has been opened. the storage conditions are 25 c, 65% rh max. caution do not use two or more soldering methods in combination (except the partial heating method). m pd75p3018a 54 data sheet u11917ej2v0ds00 appendix a. m pd75316b, 753017a and 75p3018a function list parameter m pd75316b m pd753017a m pd75p3018a program memory mask rom mask rom one-time prom 0000h-3f7fh 0000h-5fffh 0000h-7fffh (16256 8 bits) (24576 8 bits) (32768 8 bits) data memory 000h-3ffh (1024 4 bits) cpu 75x standard 75xl cpu instruction when main system 0.95, 1.91, or 15.3 m s ? 0.95, 1.91, 3.81, or 15.3 m s (at 4.19 mhz operation) execution time clock is selected (at 4.19 mhz operation) ? 0.67, 1.33, 2.67, or 10.7 m s (at 6.0 mhz operation) when subsystem 122 m s (at 32.768 khz operation) clock is selected pin connection 29 to 32 p40 to p43 p40/d0 to p43/d3 34 to 37 p50 to p53 p50/d4 to p53/d7 44 p12/int2 p12/int2/ti1/ti2 47 p21 p21/pto1 48 p22/pcl p22/pcl/pto2 50 to 53 p30 to p33 p30/md0 to p33/md3 57 ic v pp stack sbs register none sbs.3 = 1; mk i mode selection sbs.3 = 0; mk ii mode selection stack area 000h-0ffh n00h-nffh (n = 0-3) subroutine call instruction 2-byte stack mk i mode: 2-byte stack stack operation mk ii mode: 3-byte stack instruction bra !addr1 unavailable mk i mode: unavailable calla !addr1 mk ii mode: available movt xa, @bcde available movt xa, @bcxa br bcde br bcxa call !addr 3 machine cycles mk i mode: 3 machine cycles, mk ii mode: 4 machine cycles callf !faddr 2 machine cycles mk i mode: 2 machine cycles, mk ii mode: 3 machine cycles mask option yes none timer 3 channels: 5 channels: ? basic interval timer ? basic interval timer/watchdog timer: 1 channel : 1 channel ? 8-bit timer/event counter: 3 channels ? 8-bit timer/event counter (can be used as 16-bit timer/event counter, carrier generator, : 1 channel timer with gate) ? watch timer: 1 channel ? watch timer: 1 channel m pd75p3018a 55 data sheet u11917ej2v0ds00 parameter m pd75316b m pd753017a m pd75p3018a clock output (pcl) f , 524, 262, 65.5 khz ? f , 524, 262, 65.5 khz (main system clock: (main system clock: at 4.19 mhz operation) at 4.19 mhz operation) ? f , 750, 375, 93.8 khz (main system clock: at 6.0 mhz operation) buz output (buz) 2 khz ? 2, 4, 32 khz (main system clock: (main system clock: at 4.19 mhz operation or at 4.19 mhz operation) subsystem clock: at 32.768 khz operation) ? 2.93, 5.86, 46.9 khz (main system clock: at 6.0 mhz operation) serial interface 3 modes are available ? 3-wire serial i/o mode ... msb/lsb can be selected for transfer first bit ? 2-wire serial i/o mode ? sbi mode sos register feedback resistor cut flag none provided (sos.0) sub-oscillator current none provided cut flag (sos.1) register bank selection register (rbs) none yes standby release by int0 unavailable available interrupt priority selection register (ips) none yes vectored interrupt external: 3, internal: 3 external: 3, internal: 5 supply voltage v dd = 2.0 to 6.0 v v dd = 1.8 to 5.5 v operating ambient temperature t a = C40 to +85 c package ? 80-pin plastic tqfp (fine pitch) (12 12 mm) ? 80-pin plastic qfp (14 14 mm) m pd75p3018a 56 data sheet u11917ej2v0ds00 appendix b. development tools the following development tools have been provided for system development using the m pd75p3018a. in the 75xl series, the relocatable assembler common to series is used in combination with the device file of each type. ra75x relocatable assembler host machine part no. (name) os supply medium pc-9800 series ms-dos tm 3.5" 2hd m s5a13ra75x ver.3.30 to ver.6.2 note ibm pc/at tm refer to "os for 3.5" 2hc m s7b13ra75x or compatible ibm pcs" device file host machine part no. (name) os supply medium pc-9800 series ms-dos 3.5" 2hd m s5a13df753017 ver.3.30 to ver.6.2 note ibm pc/at refer to "os for 3.5" 2hc m s7b13df753017 or compatible ibm pcs" note ver. 5.00 or later includes a task swapping function, but this software is not able to use that function. remark operation of the assembler and device file is guaranteed only when using the host machine and os described above. m pd75p3018a 57 data sheet u11917ej2v0ds00 prom write tools hardware pg-1500 this is a prom programmer that can program single-chip microcontroller with prom in stand alone mode or under control of host machine when connected with supplied accessory board and optional programmer adapter. it can also program typical proms in capacities ranging from 256 k to 4 m bits. pa-75p316bgc this is a prom programmer adapter for the m pd75p3018agc-3b9. it can be used when connected to a pg-1500. pa-75p316bgk this is a prom programmer adapter for the m pd75p3018agk-be9. it can be used when connected to a pg-1500. pa-75p3018agc-8bt this is a prom programmer adapter for the m pd75p3018agc-8bt. it can be used when connected to a pg-1500. pa-75p3018agk-9eu this is a prom programmer adapter for the m pd75p3018agk-9eu. it can be used when connected to a pg-1500. software pg-1500 controller connects pg-1500 to host machine with serial and parallel interface and controls pg-1500 on host machine. host machine part no. (name) os supply medium pc-9800 series ms-dos 3.5" 2hd m s5a13pg1500 ver.3.30 to ver.6.2 note ibm pc/at refer to "os for 3.5" 2hd m s7b13pg1500 or compatible ibm pcs" note ver. 5.00 or later includes a task swapping function, but this software is not able to use that function. remark operation of the pg-1500 controller is guaranteed only when using the host machine and os described above. m pd75p3018a 58 data sheet u11917ej2v0ds00 debugging tools in-circuit emulators (ie-75000-r and ie-75001-r) are provided as program debugging tools for the m pd75p3018a. various system configurations using these in-circuit emulators are listed below. hardware ie-75000-r note 1 the ie-75000-r is an in-circuit emulator to be used for hardware and software debugging during development of application systems using the 75x or 75xl series products. for development of the m pd75p3018a, the ie-75000-r is used with optional emulation board (ie-75300-r-em) and emulation probe (ep-753018gc-r or ep-753018gk-r). highly efficient debugging can be performed when connected to host machine and prom programmer. the ie-75000-r includes a connected emulation board (ie-75000-r-em). ie-75001-r the ie-75001-r is an in-circuit emulator to be used for hardware and software debugging during development of application systems using the 75x or 75xl series products. the ie-75001-r is used with optional emulation board (ie-75300-r-em) and emulation probe (ep-753018gc-r or ep-753018gk-r). highly efficient debugging can be performed when connected to host machine and prom programmer. ie-75300-r-em this is an emulation board for evaluating application systems using the m pd75p3018a. it is used in combination with the ie-75000-r or ie-75001-r. ep-753018gc-r this is an emulation probe for the m pd75p3018agc. when being used, it is connected with the ie-75000-r or ie-75001-r and the ie-75300-r-em. ev-9200gc-80 it includes a 80-pin conversion socket (ev-9200gc-80) to facilitate connections with target system. ep-753018gk-r this is an emulation probe for the m pd75p3018agk. when being used, it is connected with the ie-75000-r or ie-75001-r and the ie-75300-r-em. tgk-080sdw note 2 it includes a 80-pin conversion adapter (tgk-080sdw) to facilitate connections with target system. software ie control program this program can control the ie-75000-r or ie-75001-r on a host machine when connected to the ie-75000-r or ie-75001-r via an rs-232-c or centronics interface. host machine part no. (name) os supply medium pc-9800 series ms-dos 3.5" 2hd m s5a13ie75x ver.3.30 to 5" 2hd m s5a10ie75x ver.6.2 note 3 ibm pc/at refer to "os for 3.5" 2hc m s7b13ie75x or compatible ibm pcs" 5" 2hc m s7b10ie75x notes 1. this is a maintenance product. 2. this is a product of tokyo eletech corporation. for further information, contact: daimaru kogyo, ltd. tokyo electronics department (tel +81-3-3820-7112) osaka electronics 2nd department (tel +81-6-6244-6672) 3. ver. 5.00 or later includes a task swapping function, but this software is not able to use that function. remark operation of the ie control program is guaranteed only when using the host machine and os described above. m pd75p3018a 59 data sheet u11917ej2v0ds00 os for ibm pcs the following operating systems for the ibm pc are supported. os version pc dos tm ver.5.02 to ver.6.3 j6.1/v to j6.3/v ms-dos ver.5.0 to ver.6.22 5.0/v to 6.2/v ibm dos tm j5.02/v caution ver. 5.0 or later includes a task swapping function, but this software is not able to use that function. m pd75p3018a 60 data sheet u11917ej2v0ds00 appendix c. related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. device related documents document no. document name japanese english m pd753012a, 753016a, 753017a data sheet u11662j u11662e m pd75p3018a data sheet u11917j u11917e (this document) m pd753017 user's manual u11282j u11282e m pd753017 instruction table iem-5598 75xl series selection guide u10453j u10453e development tool related documents document no. document name japanese english hardware ie-75000-r/ie-75001-r user's manual eeu-846 eeu-1416 ie-75300-r-em user's manual u11354j u11354e ep-753017gc/gk-r user's manual eeu-967 eeu-1495 pg-1500 user's manual u11940e u11940e software ra75x assembler package operation u12622j u12622e user's manual language u12385j u12385e pg-1500 controller user's manual pc-9800 series eeu-704 eeu-1291 (ms-dos) base ibm pc series eeu-5008 u10540e (pc dos) base other related documents document no. document name japanese english semiconductor selection guide products & package (cd-rom) x13769x semiconductor device mounting technology manual c10535j c10535e quality grades on nec semiconductor devices c11531j c11531e nec semiconductor device reliability/quality control system c10983j c10983e guide to prevent damage for semiconductor devices electrostatic c11892j c11892e discharge (esd) guide to microcontroller-related products by third parties u11416j caution the above related documents are subject to change without notice. for design purpose, etc., be sure to use the latest documents. m pd75p3018a 61 data sheet u11917ej2v0ds00 [memo] m pd75p3018a 62 data sheet u11917ej2v0ds00 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. m pd75p3018a 63 data sheet u11917ej2v0ds00 nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division rodovia presidente dutra, km 214 07210-902-guarulhos-sp brasil tel: 55-11-6465-6810 fax: 55-11-6465-6829 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j99.1 m pd75p3018a ms-dos is either a registered trademark or a trademark of microsoft corporation in the united states and/ or other countries. ibm dos, pc/at, and pc dos are trademarks of international business machines corporation. the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. m8e 00. 4 the information in this document is current as of may, 2000. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). |
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